This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS)\ntransceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge\noutput driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated\ncommon mode voltage over process, voltage and temperature (PVT) variations. The receiver was\ncomposed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common\nmode voltage shifter with an error amplifier shifted the common mode voltage of the input\nsignal to the required range, thereby the following rail-to-rail comparator obtained the maximum\ntransconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology,\nand had an area of 1.46 mm2.The measured results showed that the output swing of the transmitter\nwas around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power\nconsumption of each lane was 16.51 mW under a 1.8 V power supply.
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